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HD66704 (graphics lcd controller/driver with two 16-character lines and 160 segments) ade-207-331(z) rev 2.0 june 2001 description the HD66704 lcd controller and driver lsi is used to display alphanumeric characters, katakana, hiragana, a variety of symbols, and seven-segment numerals. it can be connected to a high-performance microcomputer via a high-speed clock-synchronized serial connection or on a four-bit bus. the HD66704 is capable of displaying two 16-character lines and 160 segments or one 16-character line and 240 segments in its character mode. the HD66704 has 432 built-in fonts for character display and supports double-height display. in its segment mode, it can drive up to 320 segments (at a duty cycle of 1/4). segment-by-segment control of a blinking state, as well as the on/off state, is available. the HD66704 applies various techniques for reducing the power consumption of an lcd system. these include low-voltage operation at 1.8 v or less, a booster to generate a maximum of triple the lcd-drive voltage from the supplied voltage, and voltage-followers to decrease the flow of direct current into the lcd- drive bleeder-resistors. the HD66704 has a slim-chip configuration and interface-signal alignment that make it appropriate for chip- on-glass (cog) mounting. it is suitable for any product in which an lcd display may be used, such as facsimiles, telephones, pagers, audio equipment, video tape recorders, and electronic wallets. features ? two 16-character lines (5-by-8-dot fonts) and 160 segments ? 320 segments with blinking control (at 1/4-duty drive) ? wide range of operating voltages ? v cc = 1.8 to 5.5 v (lcd drive voltage: v lcd = 3.0 to 6.5 v) ? double or triple step-up circuit for lcd drive voltage ? 1/2- to 1/5-bias bleeder-resistors and voltage followers for lcd-drive power supply ? 25-level electronic potentiometer ? high-speed clock-synchronized serial interface (5 mhz) and high-speed 4-bit bus interface ? continuous writing of data thanks to the zero instruction-execution time (wait-free writing) ? 80 8-bit display data ram (80 characters max) ? 17,280-bit (5 8 dots : 432 characters) character generator rom
HD66704 2 ? 16 5-bit (two characters) character generator ram ? vertical double-height display ? selectable cgrom memory bank (max. 432 fonts) ? wide range of instruction functions (in character mode): ? clear display, display on/off control, icon and mark control, character blink, black-white reversed blinking cursor, return home, cursor on/off, black-white reversed raster-row ? low-/high-speed blinking control of each segment (in segment mode) ? power-save functions such as the standby mode and sleep mode ? internal oscillation (with external or built-in resistor) hardware reset ? shift change of segment and common driver ? slim chip with bumps for chip-on-glass (cog) mounting table 1 progammable display sizes and duty ratios duty optimum drive frame frequency (at 32-khz segment mode character mode ratio bias operation) segment 7 segments character segment 1/2 1/2 88 hz 160 20 characters - - 1/3 1/3 88 hz 240 30 characters - - 1/4 1/3 88 hz 320 40 characters - - 1/11 1/4 91 hz - - 1 16-character lines 240 1/18 1/5 88 hz - - 2 16-character lines, 1 32-character line 160
HD66704 3 total current consumption characteristics (v cc = 3 v, fosc = 32 khz, typ conditions, lcd drive power current included) total power consumption normal display operation character display size duty ratio optimum drive bias frame frequency internal logic lcd power total* sleep mode standby mode segment 1/3 1/3 88 hz 15 a 15 a 45 a 11 a 0.1 a character 1/18 1/5 88 hz 20 a 15 a 50 a 11 a note : when a double booster is used: the total power consumption = internal logic current + lcd power current 2 when a triple booster is used: the total power consumption = internal logic current + lcd power current 3 type name types external dimensions operation voltages internal fonts HD66704a03bp au-bumped chip 1.8 v to 5.5 v katakana, alphanumerics, symbols, and european fonts
HD66704 4 lcd specification comparison items HD66704 hd66724 hd66725 character display sizes 16 characters x 2 lines 12 characters x 3 lines 16 characters x 3 lines graphic display sizes 72 x 26 dots 96 x 26 dots multiplexing icons 160 to 320 144 192 annunciator 1/2 to 1/4 duty 1/2 duty: 144 1/2 duty: 192 key scan control 8 x 4 8 x 4 led control ports general output ports 3 3 operating power voltages 1.8 v to 5.5 v 1.8 v to 5.5 v 1.8 v to 5.5 v liquid crystal drive voltages 3 v to 6.5 v 3 v to 6.5 v 3 v to 6.5 v serial bus clock-synchronized serial clock-synchronized serial clock-synchronized serial parallel bus 4 bits 4 bits, 8 bits 4 bits, 8 bits expansion driver control impossible impossible impossible liquid crystal drive duty ratios 1/2, 3, 4, 11, 18 1/2, 10, 18, 26 1/2, 10, 18, 26 liquid crystal drive biases 1/2 to 1/5 1/4 to 1/6.5 1/4 to 1/6.5 liquid crystal drive waveforms b b b liquid crystal voltage booster double or triple single, double or triple single, double, or triple bleeder-resistor for liquid crystal drive incorporated incorporated (external) incorporated (external) liquid crystal drive operational amplifier incorporated incorporated incorporated liquid crystal contrast adjuster incorporated incorporated incorporated horizontal smooth scroll 3-dot unit 3-dot unit vertical smooth scroll line unit line unit double-height display yes yes yes ddram 80 x 8 80 x 8 80 x 8 cgrom 17,280 20,736 20,736 cgram 16 x 5 384 x 8 384 x 8 segram 72 x 8 96 x 8 no. of cgrom fonts 240 + 192 240 + 192 240 + 192 no. of cgram fonts 2 64 64 font sizes 5 x 8 6 x 8 6 x 8 bit map area 72 x 26 96 x 26 r-c oscillation resistor/ oscillation frequency external resistor, incorporated (32 khz) external resistor, incorporated (32 khz) external resistor, incorporated (32 khz) reset function external external external low power control partial display off display off oscillation off liquid crystal power off partial display off display off oscillation off liquid crystal power off key wake-up interrupt partial display off display off oscillation off liquid crystal power off key wake-up interrupt seg/com direction switching seg, com seg, com seg, com qfp package tqfp package tcp package tcp-146 tcp-170 bare chip bumped chip yes yes yes no. of pins 126 146 170 chip sizes 8.81 x 1.79 10.34 x 2.51 10.97 x 2.51 pad intervals 70 m 80 m 80 m
HD66704 5 lcd-ii family comparison (cont) items hd66726 hd66728 character display sizes 16 characters x 5 lines 16 characters x 10 lines graphic display sizes 96 x 42 dots 112 x 80 dots multiplexing icons 192 annunciator 1/2 duty: 192 key scan control 8 x 4 8 x 4 led control ports general output ports 3 3 operating power voltages 1.8 v to 5.5 v 1.8 v to 5.5 v liquid crystal drive voltages 4.5 v to 11 v 4.5 v to 15 v serial bus clock-synchronized serial clock-synchronized serial parallel bus 4 bits, 8 bits 4 bits, 8 bits expansion driver control impossible impossible liquid crystal drive duty ratios 1/2, 10, 18, 26, 34, 42 1/8, 16, 24, 32, 40, 48, 56, 64, 72, 80 liquid crystal drive biases 1/2 to 1/8 1/4 to 1/10 liquid crystal drive waveforms b b, c liquid crystal voltage booster single, double, triple, or quadruple triple, quadruple, or quintuple bleeder-resistor for liquid crystal drive incorporated (external) incorporated (external) liquid crystal drive operational amplifier incorporated incorporated liquid crystal contrast adjuster incorporated incorporated horizontal smooth scroll vertical smooth scroll line unit line unit double-height display yes yes ddram 80 x 8 160 x 8 cgrom 20,736 20,736 cgram 480 x 8 1,120 x 8 segram 96 x 8 no. of cgrom fonts 240 + 192 240 + 192 no. of cgram fonts 64 64 font sizes 6 x 8 6 x 8 bit map areas 96 x 42 112 x 80 r-c oscillation resistor/ oscillation frequency external resistor (50 khz) external resistor (70 to 90 khz) reset function external external low power control partial display off display off oscillation off liquid crystal power off key wake-up interrupt partial display off display off oscillation off liquid crystal power off key wake-up interrupt seg/com direction switching seg, com seg, com qfp package tqfp package tcp package tcp-188 tcp-243 bare chip yes bumped chip yes yes no. of pins 188 243 chip sizes 13.13 x 2.51 13.67 x 2.78 pad intervals 100 m 70 m
HD66704 6 HD66704 block diagram system interface ? clock synchronized serial port ? four-bit bus instruction register (ir) address counter (ac) timing generator display data ram (ddram): 80 bytes character generator ram (cgram) : 80 bits character generator rom (cgrom) : 17,280 bits parallel/serial converter 80-bit latch circuit 80-bit segment shift register 18-bit bidirectional common shift register common driver lcd drive voltage selector cursor and cursor-blink controller cpg instruction decoder rs/cs* sda e/scl vcc v lcd com1/18 to com18/1 seg1/80 to seg80/1 osc1 osc2 7 8 8 5 double/triple booster c1+ 5 im2-1 reset* c1- +- +- +- +- vlout +- gnd vr rrr 0 r r test v2out v5out db1 to db3 db0/id r1 to r3 c2+ c2- character synthesis circuit 5 7 8 segment and segment-blink controller 4 8 v1 v2 v3 v4 v5 gnd v1out v3out v4out vtest segment driver
HD66704 7 HD66704 pad arrangement ? chip size: 8.81 mm 1.79 mm ? chip thickness: 550 m (typ) ? pad coordinates: pad center ? coordinate origin: chip center ? au bump size (pin number is shown in the blacket) (a) 70 m 70 m dummy1 (1), dummy2 (65), dummy8 (83), dummy9 (182), (chip corner pin) (b) 50 m 70 m gnddum (2) to vtest (64), gnd (66) to vlcd (82), seg1/80 (84) to com1/18 (181), dummy10 (183) to dummy27 (200) ? au bump pitch: 70 m (min.) ? au bump height: 20 m (typ.) ? no cross recognition mark note: although the pads for gnd, vlcd, and v cc pins are available on two sides of the chip, they are connected in the lsi. supply the power to the pads on a single side. HD66704 (top view) seg24/57 seg23/58 seg22/59 seg21/60 seg20/61 seg19/62 seg18/63 seg17/64 seg16/65 seg15/66 seg14/67 seg13/68 seg12/69 seg11/70 seg10/71 seg34/47 seg33/48 seg32/49 seg31/50 seg30/51 seg29/52 seg28/53 seg27/54 seg26/55 seg44/37 seg43/38 seg42/39 seg41/40 seg40/41 seg39/42 seg38/43 seg37/44 seg36/45 seg35/46 seg50/31 seg49/32 seg48/33 seg47/34 seg46/35 seg45/36 seg51/30 seg25/56 seg9/72 seg52/29 seg53/28 seg54/27 HD66704 type code seg55/26 seg56/25 seg57/24 seg58/23 seg59/22 seg60/21 seg61/20 seg62/19 seg63/18 seg64/17 seg65/16 seg66/15 seg67/14 seg68/13 osc1 c1+ y x seg69/12 seg70/11 seg71/10 seg72/9 seg73/8 seg74/7 seg75/6 seg76/5 seg77/4 seg78/3 seg79/2 seg80/1 c1+ c1+ c2C c2C c2+ c2+ db1 r1 r2 r3 c1C c1C c1C v lc d v lc d com13/6 com12/7 c1C c1C vlout vlout vlout vlout v lcd v lcd v lcd v lcd c2C c2C c1+ c1+ c2+ c2+ rs/cs* com11/8 com10/9 com9/10 com8/11 com7/12 com6/13 com5/14 com4/15 com3/16 com2/17 com1/18 e/scl reset* gnddum im2 im1 vccdum test sda v4out g n d g n d com14/5 com15/4 com16/3 com17/2 seg8/73 seg7/74 seg6/75 seg5/76 seg4/77 seg3/78 seg2/79 seg1/80 v cc v cc vcc vcc vcc gnd gnd gnd d um m y27 d um m y26 d um m y25 v lc d v cc c 1C c 1C c 1+ c 1+ d um m y3 d um m y4 d um m y5 d um m y6 v5out gnd v3out v2out v1out osc2 db3 db2 db0/id gnd c2+ c2C c1+ c1C vlout d um m y24 d um m y23 d um m y22 d um m y21 d um m y20 d um m y19 d um m y18 d um m y17 d um m y16 d um m y15 d um m y14 d um m y13 d um m y1 d um m y11 d um m y7 com18/1 d um m y12 d um m y2 d um m y8 d um m y9 d um m y10 vtest no.65 no.66 no.64 no.83 no.82 no.84 no.182 no.181 no.183 no.1 no.2 no.200
HD66704 8 HD66704 pad coordinates
HD66704 9 example of cog wiring ? clock-synchronized serial ? doubling-voltage booster used ? internal operational amplifier used ? internal oscillation resistor used HD66704 (top view) seg24/57 seg23/58 seg22/59 seg21/60 seg20/61 seg19/62 seg18/63 seg17/64 seg16/65 seg15/66 seg14/67 seg13/68 seg12/69 seg11/70 seg10/71 seg34/47 seg33/48 seg32/49 seg31/50 seg30/51 seg29/52 seg28/53 seg27/54 seg26/55 seg44/37 seg43/38 seg42/39 seg41/40 seg40/41 seg39/42 seg38/43 seg37/44 seg36/45 seg35/46 seg50/31 seg49/32 seg48/33 seg47/34 seg46/35 seg45/36 seg51/30 seg25/56 seg9/72 seg52/29 seg53/28 seg54/27 seg55/26 seg56/25 seg57/24 seg58/23 seg59/22 seg60/21 seg61/20 seg62/19 seg63/18 seg64/17 seg65/16 seg66/15 seg67/14 seg68/13 osc1 c1+ seg69/12 seg70/11 seg71/10 seg72/9 seg73/8 seg74/7 seg75/6 seg76/5 seg77/4 seg78/3 seg79/2 seg80/1 c1+ c1+ c2- c2- c2+ c2+ db1 r1 r2 r3 c1C c1C c1C v l c d v l c d com13/6 com12/7 c1C c1C vlout vlout vlout vlout v lcd v lcd v lcd v lcd c2- c2- c1+ c1+ c2+ c2+ rs/cs* com11/8 com10/9 com9/10 com8/11 com7/12 com6/13 com5/14 com4/15 com3/16 com2/17 com1/18 e/scl reset* gnddum im2 im1 vccdum test sda v4out g n d g n d com14/5 com15/4 com16/3 com17/2 seg8/73 seg7/74 seg6/75 seg5/76 seg4/77 seg3/78 seg2/79 seg1/80 v c c v c c v cc v cc v cc gnd gnd gnd v l c d v c c c 1 C c 1 C c 1 + c 1 + v5out gnd v3out v2out v1out osc2 db3 db2 db0/id gnd c2+ c2- c1+ c1C vlout com18/1 dummy2 dummy8 vtest sda scl cs* reset* vcc vlcd c1C c1+ gnd dummy3 dummy4 dummy5 dummy6 dummy7
HD66704 10 pin functions table 2 pin functional description signals number of pins i/o connected to functions im2, im1 2 i v cc or gnd selects the mpu interface mode: im2 im1 "gnd" "gnd" "gnd" "vcc" "vcc" "gnd" "vcc" "vcc" clock-synchronized serial interface 68-system 4-bit bus interface setting inhibited setting inhibited mpu interface mode rs/cs* 1 i mpu selects the register for a 4-bit bus interface. low: instruction high: ram access selects the HD66704 for a serial interface. low: HD66704 is selected and can be accessed high: HD66704 is not selected and cannot be accessed the start byte is transferred immediately after the signal level on this line is switched from high to low. e/scl 1 i mpu enables the data write signal for a 4-bit bus interface. high: enable inputs the serial transfer clock for a serial interface. fetches data at the rising edge of a clock. sda 1 i mpu not used for a 4-bit bus interface. fix to v cc or gnd. serves as the serial transfer data for a serial interface. db1 to db3, db0/id 4 i mpu serves as the write-only data bus for the four-bit bus interface. fix these bits to v cc or gnd when using a serial interface. since db0/id sets the id bit for a serial interface, set it to gnd or v cc to select the id. com1/18C com18/1 18 o lcd common output signals: com1 to com8 for the character display, and com9 to com11 for the segment display in the one-line character mode. com1 to com16 for the character display, and com17 and com18 for the segment display in the two-line character mode. com1 to com4 drive the lcds in the segment mode. all the unused pins output deselection waveforms. in the sleep mode (slp = 1) or standby mode (stb = 1), all pins output gnd level. the cms bit can change the shift direction of the common signal. for example, if cms = 0, com1/18 is com1. if cms = 1, com1/18 is com18.
HD66704 11 table 2 pin functional description (cont) signals number of pins i/o connected to functions seg1/80C seg80/1 80 o lcd segment output signals for segment-icon display and character/graphics display. in the sleep mode (slp = 1) or standby mode (stb = 1), all pins output gnd level. the sgs bit can change the shift direction of the segment signal. for example, if sgs = 0, seg1/80 is seg1. if sgs = 1, seg1/80 is seg80. v1outC v5out 5 o open used for output from the internal operational amplifiers. if the display quality is poor, attach a capacitor to stabilize the output. v lcd 7 power supply power supply for lcd drive. v lcd C gnd = 6.5 v max. input a voltage greater than v cc . vcc 6 power supply v cc = +1.8 v to +5.5 v gnd 8 gnd gnd (logic) = 0 v osc1, osc2 2 i or o oscillation resistor or clock for r-c oscillation using an external resistor, connect an external resistor. for r-c oscillation using an internal resistor, connect r1-r3 to osc2 and leave osc1 disconnected. for external clock supply, input clock pulses to osc1. r1Cr3 3 o osc2 for r-c oscillation using an internal resistor, adjust the internal resistor value. fluctuation of the resistor value is _30% of the reference value. care must be taken to avoid fluctuation of the frame frequency in crystal display drive operation. vlout 5 o v lcd pin/booster capacitance potential difference between v cc and gnd is boosted twice or three times and then output. c1+, c1C 16 booster capacitance external capacitance should be connected here when using the double or triple booster. c2+, c2C 10 booster capacitance external capacitance should be connected here when using the triple booster. must be left disconnected only when using the double booster. reset* 1 i mpu or external r-c circuit reset pin. initializes the lsi when low. must reset after power-on. vccdum 1 o input pins outputs the internal v cc level; shorting this pin sets the adjacent input pin to the v cc level. gnddum 1 o input pins outputs the internal gnd level; shorting this pin sets the adjacent input pin to the gnd level. test 1 i gnd test pin. must be fixed at gnd level. vtest 1 i open test pin for the operational amplifier. must be left disconnected.
HD66704 12 block function description system interface the HD66704 has two types of system interfaces: a clock-synchronized serial interface and an e-clock- synchronized 4-bit bus. the interface mode is selected by the im2/1 pin. the HD66704 has two 8-bit registers: an instruction register (ir) and a data register (dr). the ir stores instruction codes, such as clear display and display control, and address information for the display data ram (ddram) and character generator ram (cgram). the dr temporarily stores the data to be written to and read from the ddram or cgram. when rs is high, ram data can be written to the dr. the data written to the dr from the mpu is automatically written to the ddram or cgram. execution time for instruction excluding clear display is 0 clock cycle and instructions can be written in succession. address counter (ac) the address counter (ac) assigns addresses to ddram or cgram. when an address set instruction is written into the ir, the address information is sent from the ir to the ac. selection of ddram and cgram is also determined concurrently by the ram select bit (rm). after writing into (reading from) ddram or cgram, the ac is automatically incremented by 1 (or decremented by 1). the cursor display position is determined by the address counter value. display data ram (ddram) the display data ram (ddram) stores data for display as 8-bit character codes in the character display mode. its capacity is 80 8 bits, or 80 characters, which is equivalent to 20 characters 4 lines. one or two lines of character-based display can be selected by software. in the mixed display modes, the remaining two- or three-line ddram, which is not used for the character display, is used for 160- or 240-segment displays. the segment display mode allows control of 320 segments. in all three modes, the assignment of ddram addresses is the same for all display modes. the display data ram (ddram) stores data that indicates whether each segment is light or dark, and whether it should blink. in segment-only mode, it carries display data for 80 segments 4 common lines since two bits of information are required per segment.
HD66704 13 character generator rom (cgrom) the character generator rom (cgrom) generates 5 8-dot character patterns from 8-bit character codes. it is equipped with a memory bank to generate 240 character patterns or 192 character patterns, which can be switched according to applications. for details, see the cgrom bank switching function section. tables 8 and 9 illustrate the relation between character codes and character patterns for the hitachi standard cgrom. user-defined character patterns are also available using a mask-programmed rom (see the modifying character patterns section). the cgrom cannot be used for the segment mode. character generator ram (cgram) the character generator ram (cgram) allows the user to redefine the character patterns in the character mode. two character patterns of 5 8-dot characters can be simultaneously displayed. the ddram- specified character code can be selected to display one of these user font patterns. the cgram cannot be used for the segment mode. timing generator the timing generator generates timing signals for the operation of internal circuits such as ddram, cgrom, and cgram. the ram read timing for display and internal operation timing by mpu access are generated separately to avoid interference with one another. this prevents flickering in areas other than the display area when writing the data to the ddram, for example. cursor/blink control circuit the cursor/blink (or black-white reversed) control is used to create a cursor or a flashing area on the display in a position corresponding to the location stored in the address counter (ac). note: the cursor/blink or black-white reversed control is also active when the address counter indicates the cgram. however, it has no effect on the display. 00 01 02 03 04 05 06 07 08 09 0a 1 2 3 4 5 6 7 8 9 10 11 cursor position display position ddram address 0b 12 figure 1 cursor position and ddram address (when ac = 08h)
HD66704 14 oscillation circuit (osc) the HD66704 can provide r-c oscillation simply through the addition of an external oscillation-resistor between the osc1 and osc2 pins. the appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. internal resistors can be used for r-c oscillation. if this is done, care must be taken due to variations in the oscillation frequency caused by fluctuations in internal-resistor values. clock pulses can also be supplied externally. since r-c oscillation stops during the standby mode, current consumption can be reduced. for details, see the oscillation circuit section. liquid crystal display driver circuit the liquid crystal display driver circuit consists of 18 common signal drivers (com1 to com18) and 80 segment signal drivers (seg1 to seg80). when the number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output deselection waveforms. the character pattern data is sent serially through a 80-bit shift register and latched when all needed data has arrived. the latched data then enables the segment signal drivers to generate drive waveform outputs. the shift direction of 80-bit data can be changed by the sgs bit. the shift direction for the common driver can also be changed by the cms bit by selecting an appropriate direction for the device mounting configuration. when multiplexing drive is not used, or during the standby or sleep mode, all the above common and segment signal drivers output the gnd level, halting the display. booster (dc-dc converter) the booster doubles or triples a voltage input to the v cc pin. with this, both the internal logic units and lcd drivers can be controlled with a single power supply. for details, see the power supply for liquid crystal display drive section. v-pin voltage follower a voltage follower for each voltage level (v1 to v5) reduces current consumption by the lcd drive power supply circuit. no external resistors are required because of the internal bleeder-resistor, which generates different levels of lcd drive voltage. this internal bleeder-resistor can be software-specified from 1/2 bias to 1/5 bias, according to the liquid crystal display drive duty value. the voltage followers can be turned off while multiplexing drive is not being used. for details, see the power supply for liquid crystal display drive section. contrast adjuster the contrast adjuster can be used to adjust lcd contrast in 25 steps by varying the lcd drive voltage by software. this can be used to select an appropriate lcd brightness or to compensate for temperature.
HD66704 15 ddram address map table 3 ddram addresses and display positions in character mode (nl2 = 1) display line display digit note: 1. when one line of characters is displayed (nl2-0 = 100), the ddram area for the second to fourth lines produces a segment-based display. when two lines of characters are displayed (nl2-0 = 101/110), the ddram area for the third to fourth lines produces a segment-based display. when nl2-0 = 110, the font display in the second line is mirror-inverted. 2. when sgs = 0, seg1/80 to seg5/76 appear at the first character at the extreme left of the screen. when sgs = 1, seg80/1 to seg76/5 appear at the first character at the extreme left of the screen. 3. the 17th to 20th characters are not displayed. "00" 123456789101112 first line second line third line fourth line "20" "01" "21" "02" "22" "03" "23" "04" "24" "05" "25" "06" "26" "07" "27" "08" "28" "09" "29" "0a" "2a" "0b" "2b" 13 "0c" "2c" 14 "0d" "2d" 15 "0e" "2e" 16 "0f" "2f" "40" "41" "42" "43" "44" "45" "46" "47" "48" "49" "4a" "4b" "4c" "4d" "4e" "4f" (note 3) (note 1) 17 "10" "30" "50" 18 "11" "31" "51" 19 "12" "32" "52" 20 "13" "33" "53" "60" "61" "62" "63" "64" "65" "66" "67" "68" "69" "6a" "6b" "6c" "6d" "6e" "6f" "70" "71" "72" "73" table 4 character display line and ddram addresses display line duty display common pin ddram address one-line mode 1/11 character com1-8 00h to 13h (nl = 100) segment com9 20h to 33h com10 40h to 53h com11 60h to 73h two-line mode 1/18 character com1-8 00h to 13h (nl = 101) com9-16 20h to 33h segment com17 40h to 53h com18 60h to 73h
HD66704 16 table 5 ddram addresses and display positions in segment mode (nl2 = 0) common segment "00" 1-4 5-8 9-12 13-16 17-20 21-24 25-28 29-32 33-36 37-40 41-44 45-48 com1 com2 com3 com4 note: 1. when sgs = 0, seg1/80 pin is seg1. when sgs = 1, seg80/1 pin is seg1. 2. com1 and com2 are used for a duty cycle of 1/2. com1, com2, and com3 are used for a duty cycle of 1/3. "20" "01" "21" "02" "22" "03" "23" "04" "24" "05" "25" "06" "26" "07" "27" "08" "28" "09" "29" "0a" "2a" "0b" "2b" 49-52 "0c" "2c" 53-56 "0d" "2d" 57-60 "0e" "2e" 61-64 "0f" "2f" "40" "41" "42" "43" "44" "45" "46" "47" "48" "49" "4a" "4b" "4c" "4d" "4e" "4f" 65-68 "10" "30" "50" 69-72 "11" "31" "51" 73-76 "12" "32" "52" 76-80 "13" "33" "53" "60" "61" "62" "63" "64" "65" "66" "67" "68" "69" "6a" "6b" "6c" "6d" "6e" "6f" "70" "71" "72" "73" table 6 ddram data and segment display at no blinking (sb = 0) d5 d4 0 1 0 (always light) 1 (always dark) d6 d7 note: 1. after the upper four bits have been written to a location, the ac is automatically incremented or decremented by 1. 2. any setting in the four lower-order bits (d3 to d0) is ignored. 0 1 0 1 0 1 seg1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 73, 77 seg2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 78 seg3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59, 63, 67, 71, 75, 79 seg4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80 segment driver segment lcd-display control ddram data settin
HD66704 17 table 7 ddram data and segment display at blinking (sb = 1) d5 d1 d4 d0 00 01 10 11 ddram data setting 0 (always light) 1 (always dark) d2 d6 d3 d7 note: 1. blinking is the repeated activation (darkening) or deactivation (lightening) of a segment for 32 or 64 frames. the blinking cycle (number of frames) is selected by the bl bit. 2. during a blink in normal mode, the segment is activated (darkened). in inverse mode, it is deactivated (lightened). 00 01 10 11 00 01 10 11 00 01 10 11 seg1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 73, 77 seg2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 78 seg3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59, 63, 67, 71, 75, 79 seg4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80 segment driver (note 1) (note 2) blinking display blinking display in inverse mode segment lcd-display control
HD66704 18 table 8 cgrom memory bank 0 (rom bit = 0)
HD66704 19 table 9 cgrom memory bank 1 (rom bit = 1)
HD66704 20 cgram address map table 10 relationship between character mode and cgram address "96"h "00"h "01"h "02"h "03"h "04"h "05"h "06"h "07"h "08"h "09"h "0a"h "0b"h "0c"h "0d"h character code cgram address (hex) character code note: in the character mode, cgram font pattern is displayed using character codes set to ddram as per the above table. cgram address (hex) font bank font bank memory bank: rom = 0, 1 memory bank: rom = 1 "90"h "91"h "92"h "93"h "94"h "95"h "97"h "98"h "99"h "9a"h "9b"h "9c"h "9d"h "0e"h "9e"h "0f"h "9f"h "10"h "11"h "12"h "13"h "14"h "15"h "16"h "17"h "18"h "19"h "1a"h "1b"h "1c"h "1d"h "1e"h "1f"h "80"h "81"h "82"h "83"h "84"h "85"h "86"h "87"h "88"h "89"h "8a"h "8b"h "8c"h "8d"h "8e"h "8f"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h "08"h to "0f"h "00"h to "07"h table 11 relationship between cgram address and character pattern (cgram data) d4 d3 d2 d1 d0 d4 d3 d2 d1 d0 "00"h "01"h "02"h "03"h "04"h "05"h "06"h "07"h notes: 1. the 8th raster-row is the cursor position and its display is formed by a logical or with the cursor. 2. a set bit in the cgram data corresponds to display selection 1 (darkened) and 0 to non-selection (lightened). 0 1 1 1 1 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 cgram address character code "00"h "01"h "08"h "09"h "0a"h "0b"h "0c"h "0d"h "0e"h "0f"h cgram address character code
HD66704 21 modifying character patterns character pattern development procedure start user create eprom address and data listing write eprom eprom hitachi computer processing create character pattern listing art work evaluate character patterns masking trial sample ok ? sample evaluation mass production (2) (1) (3) (4) (5) (6) no no yes yes determine character patterns ok ? hitachi figure 2 character pattern development procedure the following operations correspond to the numbers listed in figure 2: 1. determine the correspondence between character codes and character patterns. 2. create a listing indicating the correspondence between eprom addresses and data. 3. program the character patterns into an eprom. 4. send the eprom to hitachi.
HD66704 22 5. computer processing of the eprom is performed at hitachi to create a character pattern listing, which is sent to the user. 6. if there are no problems within the character pattern listing, a trial lsi is created at hitachi and samples are sent to the user for evaluation. when the user confirms that the character patterns are correctly written, hitachi will commence lsi mass production.
HD66704 23 programming character patterns this section explains the correspondence between addresses and data used to program character patterns in eprom. programming to eprom: the HD66704 character generator rom can generate 432 5 8-dot character patterns. table 12 shows the correspondence between the eprom address, data, and the character pattern. table 12 examples of correspondence between eprom address, data, and character pattern (5 8 dots) a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 000 00 1 010 011 100 101 11 0 11 1 0 0 1 1 0 1 0 1 000 1 o 4 o 3 o 2 o 1 o 0 10001 10001 01 0 1 0 00100 00100 00 1 00 00000 character code line position eprom address data lsb msb a 11 0 0 0 0 0 0 0 0 0 a 12 0 rom bit notes: 1. eprom address: bit a12 corresponds to the cgrom memory bank switch bit ("rom"). 2. eprom address: bits a11 to a4 correspond to a character code. 3. eprom address: bits a2 to a0 specify the line position of the character pattern. eprom address bit a3 must be set to 0. 4. eprom data: bits o4 to o0 correspond to character pattern data. 5. areas which are darkened (indicated by shading) are stored as 1, and lightened areas as 0. 6. the eighth raster-row is also stored in the cgrom, and must also be programmed. if the eighth raster-row is used for a cursor, this data must all be set to zero. 7. eprom data: bits o7 to o5 are invalid. 0 must be written in all bits. handling unused character patterns: 1. eprom data outside the character pattern area: this is ignored by character generator rom for display operation so any data is acceptable. 2. eprom data in cgram area: always fill with zeros. 3. treatment of unused user patterns in the HD66704 eprom: depending on to the user application, these are handled in either of two ways: a. when unused character patterns are not programmed: if an unused character code is written into ddram, all its dots are darkened, because the eprom is filled with 1s after it is erased.
HD66704 24 b. when unused character patterns are programmed as 0s: nothing is displayed even if unused character codes are written into ddram. (this is equivalent to a space.)
HD66704 25 instructions outline only the instruction register (ir) and the data register (dr) of the HD66704 can be controlled by the mpu. before starting internal operation of the HD66704, control information is temporarily stored in these registers to allow interfacing with various peripheral control devices or mpus which operate at different speeds. the internal operation of the HD66704 is determined by signals sent from the mpu. these signals, which include the register selection signal (rs) and the data bus signals (d7 to d0), make up the HD66704 instructions. there are four categories of instructions that: ? control the display ? control power management ? set internal ram addresses ? write data to the internal ram normally, instructions that perform data transfer with the internal ram are used the most. however, auto- incrementation by 1 (or auto-decrementation by 1) of internal HD66704 ram addresses after each data write can lighten the mpu program load. because instructions other than clear display instruction are executed in 0 cycle, instructions can be written in succession. while the clear display instruction is being executed for internal operation, or during reset, no instruction other than the key scan read instruction can be executed.
HD66704 26 instruction descriptions clear display the clear display instruction writes space code 20h (the character pattern for character code 20h must be a blank pattern) into all ddram addresses. it then sets ddram address 0 into the address counter. it also sets i/d to 1 (increment mode) in the entry mode set instruction. since the execution of this instruction needs 85 clock cycles, do not send the next instruction during the execution time. in segment mode, if 20h is explicitly written to the ddram after the display has been cleared, the result will be the activation (darkening) of a segment. rs d7 d0 0 d6 d5 d4 d3 d2 d1 00000001 figure 3 clear display instruction return home the return home instruction sets ddram address 0 into the address counter. the ddram contents do not change. the cursor or blinking goes to the top left of the display. rs d7 d0 0 d6 d5 d4 d3 d2 d1 00000010 figure 4 return home instruction start oscillation the start oscillation instruction restarts the oscillator from the halt state in the standby mode. after issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (refer to the standby mode section.) rs d7 d0 0 d6 d5 d4 d3 d2 d1 00000011 figure 5 start oscillation instruction
HD66704 27 driver output control cms: selects the output shift direction of a common driver. when cms = 0, com1/18 shifts to com1, and com18/1 to com18. when cms = 1, com1/18 shifts to com18, and com18/1 to com1. output position of a common driver shifts depending on the cen bit setting. for details, see the display on/off control section. sgs: selects the output shift direction of a segment driver. when sgs = 0, seg1/80 shifts to seg1, and seg80/1 to seg80. when sgs = 1, seg1/80 shifts seg80, and seg80/1 to seg1. rs d7 d0 0 d6 d5 d4 d3 d2 d1 000001cms initial value cms = "0" sgs = "0" sgs figure 6 driver output control instruction power control amp: when amp = 1, each voltage follower for the v1 to v5 pins and the booster are turned on. when amp = 0, current consumption can be reduced when the display is not being used. slp: when slp = 1, the HD66704 enters the sleep mode, where the internal operations are halted except for the r-c oscillator, thus reducing current consumption. for details, refer to the sleep mode section. only the power-control instructions (amp, slp, and stb bits) can be executed during the sleep mode. during the sleep mode, the other ram data and instructions cannot be updated although they are retained. stb: when stb = 1, the HD66704 enters the standby mode, where all the internal operations including the internal r-c oscillator completely stop. for details, refer to the standby mode section. only the following instructions can be executed during the standby mode. a. standby mode cancel (stb = 0) b. voltage follower circuit on/off (amp = 1/0) c. start oscillator during the standby mode, the other ram data and instructions may be lost. to prevent this, they must be set again after the standby mode is canceled. rs d7 d0 0 d6 d5 d4 d3 d2 d1 00001ampslpstb initial value amp = "0" slp = "0" stb = "0" figure 7 power control instruction
HD66704 28 contrast control 1/2 sw: switches the bit configuration for the contrast control instruction. sw = 0 corresponds to ct2 to ct0. sw = 1 corresponds to bt and bs1 to bs0. ct4Cct0: when sw = 0 controls the lcd drive voltage (potential difference between v1 and gnd) to adjust contrast. a 25-step adjustment is possible. for details, refer to the contrast adjuster section. bt1-0: when sw = 1, it selects the output factor for boosting. when bt = 0, it doubles boosting. when bt = 1, it triples boosting. bs1-0: when sw = 1, it sets the crystal display drive bias value within the range of 1/2 to 1/5 bias. the liquid crystal display drive bias value can be selected according to its drive duty ratio and voltage. for details, see the liquid crystal display drive bias selector circuit section. rs d7 d0 0 d6 d5 d4 d3 d2 d1 00010swct4ct3 000011 ct1 ct0 bs1 bs0 (sw = "0") (sw = "1") ct2 bt initial value bt = "0" bs1/0 = "00" ct4C0 = "00000" figure 8 contrast control 1/2 instruction v lcd v1 v2 v3 v4 v5 vr r r r 0 r r gnd HD66704 gnd C + C + C + C + C + figure 9 contrast adjuster
HD66704 29 table 13 ct bits and variable resistor value of contrast adjuster ct set value variable ct set value variable ct4 ct3 ct2 ct1 ct0 resistor (vr) ct4 ct3 ct2 ct1 ct0 resistor (vr) 0 0 0 0 0 2.5 x r (initial value) 1 0 0 0 0 1.6 x r 0 0 0 0 1 2.5 x r 1 0 0 0 1 1.5 x r 0 0 0 1 0 2.5 x r 1 0 0 1 0 1.4 x r 0 0 0 1 1 2.5 x r 1 0 0 1 1 1.3 x r 0 0 1 0 0 2.5 x r 1 0 1 0 0 1.2 x r 0 0 1 0 1 2.5 x r 1 0 1 0 1 1.1 x r 0 0 1 1 0 2.5 x r 1 0 1 1 0 1.0 x r 0 0 1 1 1 2.5 x r 1 0 1 1 1 0.9 x r 0 1 0 0 0 2.4 x r 1 1 0 0 0 0.8 x r 0 1 0 0 1 2.3 x r 1 1 0 0 1 0.7 x r 0 1 0 1 0 2.2 x r 1 1 0 1 0 0.6 x r 0 1 0 1 1 2.1 x r 1 1 0 1 1 0.5 x r 0 1 1 0 0 2.0 x r 1 1 1 0 0 0.4 x r 0 1 1 0 1 1.9 x r 1 1 1 0 1 0.3 x r 0 1 1 1 0 1.8 x r 1 1 1 1 0 0.2 x r 0 1 1 1 1 1.7 x r 1 1 1 1 1 0.1 x r table 14 bs bits and lcd drive bias value bs1 bs0 liquid crystal display drive bias value 0 0 1/5 bias drive (initial value) 0 1 1/4 bias drive 1 0 1/3 bias drive 1 1 1/2 bias drive entry mode set rom: switches the cgrom memory bank in the character mode (nl2 = 1). uses bank 0 for display when rom = 0 and bank 1 for display when rom = 1. for details, see the cgrom bank switching function section. i/d: increments (i/d = 1) or decrements (i/d = 0) the ddram address by 1 when a character code is written into ddram. the cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. the same applies to the writing of cgram.
HD66704 30 sb: switches blinking of the segment display on and off. when sb = 0, the segments do not blink, and the data for display is more efficiently written by only using the upper four bits (d7 to d4) of the ddram. when sb = 1, blinking is enabled for any segment, and two bits of display data is used for each segment by using all eight bits of each byte in the ddram. in character mode (nl2 = 1), be sure to set sb to 1. for details, see the segment display function section. rs d7 d0 0 d6 d5 d4 d3 d2 d1 00100romi/dsb initial value rom = "0" i/d = "1" sb = "0" figure 10 entry mode set instruction cursor control b/w : when b/w = 1 and lc = 0, the character at the cursor position is cyclically blink-displayed with black-white inversion. the blinking cycle is selected by the bl bit in the display on/off control register. when b/w = 1 and lc = 1, all characters including the cursor on the display line appear with black-white inversion. the characters do not blink. for details, refer to the line-cursor display section. c: the cursor is displayed on the 8th raster-row when c = 1. the 5-dot cursor is ored with the character pattern and displayed on the 8th raster-row. b: the character indicated by the cursor blinks when b = 1 in the character mode (nl2 = 1). the blinking is displayed as switching between all black dots and displayed characters when b/w = 0. when b/w = 1, cursor blinking switches between all white dots and the display of the character at the cursor position. the cursor in the 8th raster-row and blinking can be set for simultaneous display. the blinking cycle is selected by the bl bit in the display on/off control register. rs d7 d0 0 d6 d5 d4 d3 d2 d1 00101b/wcb initial value $! c = "0" b = "0" figure 11 cursor control instruction
HD66704 31 alternating display alternating display (ii) 8th raster-row cursor display (when c = 1) (iii) blink display example (1) (when lc = 0, b/w = 0, b = 1) (iv) blink display example (2) (when lc = 0, b/w = 1, b = 1) alternating display (i) black-white reversed display example (when lc = 0, b/w = 1) figure 12 cursor control examples display on/off control d: display is on when d = 1 and off when d = 0. when off, the display data remains in ddram, and can be displayed instantly by setting d to 1. when d is 0, the display is off with the seg1 to seg72 (96) outputs, com1 to com24 outputs, and coms1/2 output set to the gnd level and off. because of this, the HD66704 can control charging current for the lcd with ac driving. bl: sets the blinking cycle in the character and segment modes. the display is switched every 32 frames when bl = 0. it is also switched every 64 frames when bl = 1. lc: when lc = 1, a cursor attribute is assigned to the line that contains the address counter (ac) value. cursor mode can be selected with the b/w, c, and b bits. refer to the line-cursor display section. rs d7 d0 0 d6 d5 d4 d3 d2 d1 00110dbllc initial value bl = "0" lc = "0" figure 13 display on/off control instruction
HD66704 32 display line control nl2-0: specifies the display lines. display lines change the liquid crystal display drive duty ratio. ddram address mapping does not depend on the number of display lines. when nl = 110, the character fonts from the cgrom/cgram are mirror-inverted for display on the second line alone. wiring on the lcd glass is used to display one 32-character line. for details, see the lcd panel interface section. rs d7 d0 0 d6 d5 d4 d3 d2 d1 00111nl2nl1nl0 initial value nl2C0 = "101" figure 14 display line control instruction table 15 nl bits and display lines nl2 nl1 nl0 display lines liquid crystal display drive duty ratio common driver used 0 0 0 1/2-duty segment 1/2 duty com1 to com2 0 0 1 1/3-duty segment 1/3 duty com1 to com3 0 1 0 1/4-duty segment 1/4 duty com1 to com4 0 1 1 setting inhibited - - 1 0 0 one character line + segment display 1/11 duty com1 to com11 1 0 1 two character lines + segment display 1/18 duty com1 to com18 (initial value) 1 1 0 two character lines + segment display (fonts in the second line are horizontally inverted) 1/18 duty com1 to com18 double-height display control dl: when dl = 1, the first line is displayed at double height. do not insert a space between the first and second lines when the double-height display function is used. for details, see the double-height display section. rs d7 d0 0 d6 d5 d4 d3 d2 d1 0100000dl initial value figure 15 double-height display control instruction
HD66704 33 blink synchronization initializes the blink counter to control the blinking cycle of the cursor or segment. after initialization, be sure to lighten the display. when this instruction is issued every second, the blinking cycle will be one second, in dependent of the lcd frame frequency. when the blinking is synchronized every second and the frame frequency is near 100 hz, make the display blink for 64 frames by setting bl to 1. rs d7 d0 0 d6 d5 d4 d3 d2 d1 01110000 figure 16 blink synchronization instruction ram address set rm: selects ddram and cgram. the selected ram is accessed with this setting. ad6-0: initially sets ram addresses to the address counter (ac). once ram data is accessed, the ac is automatically updated according to the i/d bit. this allows consecutive accesses without resetting addresses. ram address setting is not allowed in the sleep mode or standby mode. rs d7 d0 0 d6 d5 d4 d3 d2 d1 10rm0000ad6 0 1 1 ad5 ad4 ad3 ad2 ad1 ad0 figure 17 ram address set instruction table 16 ad bits and ddram setting rm ad6-ad0 ddram setting 0 "00"h-"13"h display data on the 1st line 0 "20"h-"33"h display data on the 2nd line 0 "40"h-"53"h display data on the 3rd line 0 "60"h-"73"h display data on the 4th line table 17 ad bits and cgram setting rm ad3-ad0 cgram setting 1 "0"h-"7"h font data of cgram (1) 1 "8"h-"f"h font data of cgram (2)
HD66704 34 write data to ram wd7-0 : writes 8-bit data to ddram and cgram. ddram or cgram is selected by the previous specification of the rm bit. after a write, the address is automatically incremented or decremented by 1 according to the i/d bit setting in the entry mode set instruction. during the sleep and standby modes, ddram or cgram cannot be accessed. rs d7 d0 1 d6 d5 d4 d3 d2 d1 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 figure 18 write data to ram instruction
HD66704 35 table 18 instruction list exe- register code cution name rs d7 d6 d5 d4 d3 d2 d1 d0 description cycle* nop 000 0000 00 no operation. no processing is executed. 0 clear display 0 0 0 0 0 0 0 0 1 clears entire display and sets address 0 into the address counter (ac). 85 return home 0 0 0 0 0 0 0 1 0 sets ddram address 0 into the address counter (ac). 0 start oscillator 0 0 0 0 0 0 0 1 1 starts the oscillation standby mode. driver output control 0 0 0 0 0 0 1 cms sgs selects the common driver shift direction (cms) and segment driver shift direction (sgs). 0 power control 0 0 0 0 0 1 amp slp stb turns on lcd power supply (amp), and sets the sleep mode (slp) and standby mode (stb). 0 contrast control 1 0 0 0 0 1 0 sw ct4 ct3 sets the register selection (sw) or upper contrast adjustment bits (ct4-3). 0 contrast control 2 0 0 0 0 1 1 ct2 ct1 ct0 sets the lower contrast 0 bt bs1 bs0 adjustment bits (ct2-0), step-up factor (bt), or lcd bias value (bs1-0). entry mode set 0 0 0 1 0 0 rom i/d sb sets the cgrom memory bank switching (rom), address update direction (i/d), and segment blink control (sb). 0 cursor control 0 0 0 1 0 1 b/w c b sets black-white inverting cursor (b/w), 8th raster-row cursor (c), and blink cursor (b). 0 display on/off control 0 0 0 1 1 0 d bl lc sets display on (d), blinking cycle (bl), and line cursor display (lc). 0 display line control 0 0 0 1 1 1 nl2 nl1 nl0 sets the number of display lines (drive duty). 0 double-height display control 0 0 1 0 0 0 0 0 dl specifies double-height display lines (dl). 0 blink synchronization 0 0 1 1 1 0 0 0 0 synchronizes the blink counter. 0 ram address set (upper bits) 010 rm00 0 0ad6 (upper bit) sets the ram selection (rm) and most upper ram address (ad6) to the ddram. 0
HD66704 36 table 18 instruction list (cont) exe- register code cution name rs d7 d6 d5 d4 d3 d2 d1 d0 description cycle* ram address set (lower bits) 0 1 1 ad5-0 (lower bits) sets the initial lower ram addresses (ad5-0) to the address counter (ac). 0 write data to ram 1 write data writes data to ddram or cgram. 0 note: represented by the number of operating clock pulses; the execution time depends on the supplied clock frequency or the internal oscillation frequency. bit definition: cms = 0: com1/18 => com1 sgs = 0: seg1/80 => seg1 amp = 1: operational amplifier and booster circuit on slp = 1: sleep mode stb = 1: standby mode sw = 0: ct4-0 access/sw = 1: bs2-0 access ct4-0: contrast adjustment bt = 0: boost level selection (0: double, 1: triple) bs1-0: lcd drive bias selection (00: 1/5, 01: 1/4, 10: 1/3, 11: 1/2) rom = 0: cgrom bank 0 selection/rom = 1: cgrom bank 1 selection id = 1: address increment id = 0: address decrement sb = 0: no segment blink sb = 1: segment blink b/w = 1: black-white inverting cursor on c = 1: 8th raster-row cursor on b = 1: blink cursor on d = 1: display on bl = 0: blink every 32 frames bl = 1: blink every 64 frames lc = 1: cursor display for the all display lines including ac nl2-0: drive duty setting (000: 1/2 duty ratio, 001: 1/3 duty ratio, 010: 1/4 duty ratio, 100: 1/11 duty ratio, 101/110: 1/18 duty ratio) dl = 1: double-height display for the first line rm: ram selection (0: ddram, 1: cgram) add6-0: ddram/cgram address set (ddram: 00h-73fh, cgram: 0h-fh)
HD66704 37 reset function the HD66704 is internally initialized by reset input. during initialization, the system executes a clear display instruction after reset is canceled. the system executes the other instructions during the reset period. because the busy flag (bf) indicates a busy state (bf = 1) during the reset period and execution of the clear display instruction following reset cancellation, no instruction or ram data access from the mpu is accepted. here, reset input must be held back for at least 1 ms, and an issuing instruction must wait for 500 clock cycles after reset is canceled because the display clearing continues after reset cancellation. when this function is used in the character mode (nl2 = 1) and the ddram contains character code data, set sb = 1. instruction set initialization: 1. clear display executed (writes 20h to ddram) 2. return home executed (sets the address counter (ac) to 00h to select ddram) 3. start oscillator executed 4. driver output control (sgs = 0, cms = 0) 5. power control (amp = 0: lcd power off, slp = 0: sleep mode off, stb = 0: standby mode off) 6. double boost (bt = 0), 1/5 bias drive (bs1/0 = 00), weak contrast (ct4-0 = 00000) 7. entry mode set (rom = 0: cgrom bank 0, i/d = 1: increment by 1, sb = 0: no segment blinking) 8. cursor display off (b/w = 0, c = 0, b = 0) 9. display on/off control (d = 0: display off, bl = 0: 32-frame blinking, lc = 0: line-cursor off) 10. display control (nl2/1/0 = 101: 1/18 duty ratio) 11. double-height display off (dl = 0) ram data initialization: 1. ddram all addresses are initialized to 20h by the clear display instruction after the reset is canceled. 2. cgram this is not automatically initialized by reset input but must be initialized by software while display is off (d = 0) output pin initialization: 1. lcd driver output pins (seg/com): outputs gnd level 2. booster output pins (vlout): outputs v cc level 3. oscillator output pin (osc2): outputs oscillation signal
HD66704 38 clock-synchronized serial interface setting the im1 and im2 pins (interface mode pins) to the gnd level allows standard clock-synchronized serial data transfer, using the chip select line (cs*), serial data line (sda), and serial transfer clock line (scl). for a serial interface, the db0/id pin function uses an id pin. the HD66704 initiates serial data transfer by transferring the start byte at the falling edge of cs* input. they end serial data transfer at the rising edge of cs* input. the HD66704 is selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit device identification code assigned to the HD66704. the HD66704, when selected, receives the subsequent data string. the least significant bit of the identification code can be determined by the id pin. the five upper bits must be 01110. two different chip addresses must be assigned to a single HD66704 because the seventh bit of the start byte is used as a register select bit (rs): that is, when rs = 0, an instruction can be issued, and when rs = 1, the data can be written to ram. therefore, assign two chip addresses to one HD66704. be sure to set 0 to the eighth bit of the start byte (r/w bit) as shown in table 19. after receiving the start byte, the HD66704 receives or transmits the subsequent data byte-by-byte. the data is transferred in the msb-first format. to transfer the data consecutively, note that only the display- clear instruction requires a longer execution time than the others (see table 18). table 19 start byte format transfer bit s 12345678 start byte format transfer start device id code rs 0 01110id note: the id bit is selected by the db0/id pin. table 20 rs bit function of clock-synchronized serial interface data rs function 0 writes instruction 1 writes ram data
HD66704 39 a) basic data-transfer timing through clock-synchronized serial bus interface start byte instruction, ram data scl (input) cs * (input) transfer start transfer end start byte instruction 1 execution time scl (input) b) consecutive data-transfer timing through clock-synchronized serial bus interface 12345678910111213141516 171819 instruction 1 instruction 2 20 21 22 23 24 25 26 27 28 29 30 31 32 instruction 2 execution time instruction 3 start end note: when instruction 1 is a clear display instruction, adjust the transfer rate so that the 8th bit of instruction 2 is transferred after execution of the clear display instruction. cs * (input) sda (input/ output) sda (input/ output) 1234 5678910111213141516 d7 d6 d5 d4 "0" device id code id rs d3 d2 d1 d0 msb rs "1" "1" "0" "1" "0" lsb figure 19 clock-synchronized serial interface timing sequence
HD66704 40 4-bit bus interface setting the im2-1 (interface mode) to the gnd/v cc level allows 68-system 4-bit bus interface (db3 to db0). a direct interface using the 4-bit e-clock-synchronized bus or an interface via the i/o bus can be established. 8-bit instructions and ram data are divided into four upper bits (d7 to d4) and lower bits (d3 to d0) and transfer starts. c0 c1 a0 - a3 e rs db0 - db3 h8/325 HD66704 4 * interface via i/o port figure 20 interface to 4-bit microcomputer the HD66704 supports transfer synchronization function which resets the upper/lower counter to count upper/lower four-bit data transfer in the 4-bit bus interface. noise causing transfer mismatch between the four upper and lower bits can be corrected by a reset triggered by consecutively writing a 0000 instruction (nop) four times. the next transfer starts from the upper four bits. executing synchronization function periodically can recover any runaway in the display system. "0000" "0000" "0000" "0000" rs e db3 -db0 upper lower 4-bit transfer synchronization (1) (2) (3) (4) upper/ lower (d3-d0) (d7-d4) figure 21 4-bit transfer synchronization
HD66704 41 oscillator circuit the HD66704 can either be supplied with operating pulses externally (external clock mode), oscillate using an internal cr oscillator with an external oscillator-resistor (external resistor oscillation mode), or oscillate using an internal oscillator-resistor (internal resistor oscillation mode). internal oscillator-resistors fluctuate by 30% depending on products. avoid frame frequency fluctuations as these affect video quality. to prevent these, use an external resistor. 1) external clock mode 2) external resistor oscillation mode osc1 osc1 osc2 clock (32 khz) rf the oscillator frequency can be adjusted by oscillator resistor (rf). if rf is increased or power supply voltage is decreased, the oscillator frequency decreases. for the relationship between rf resistor value and oscillation frequency, see the electric characteristics footnote section. HD66704 HD66704 3) internal resistor oscillation mode osc1 osc2 rf 0 (=650 k ? /typ.) HD66704 rf 1 (=150 k ? /typ.) rf 2 (=100 k ? /typ.) r1 r2 r3 note that the internal resistors rf0, rf1, and rf2 fluctuate by 30% depending on products. i) r1 - osc2 short-circuiting rf = rf = 650 k ? (typ.) ii) r1 - r2 short-circuiting, r3-osc2 short-circuiting rf = rf + rf = 750 k ? (typ.) iii) r2 - osc2 short-circuiting rf = rf + rf = 800 k ? (typ.) iv) r3 - osc2 short-circuiting rf = rf + rf + rf = 900 k ? (typ.) 0 0 2 0 1 012 figure 22 oscillator circuits table 21 multiplexing duty ratio and lcd frame frequency (fosc = 32 khz) segment display one character line two character lines nl = 000 nl = 001 nl = 010 nl = 100 nl = 101/110 drive duty 1/2 1/3 1/4 1/11 1/18 total clocks/frame 360 360 360 352 360 frame frequency 88 hz 88 hz 88 hz 91 hz 88 hz
HD66704 42 1 2 3 4 17 181 2 3 17 18 v1 v2 v5 gnd com1 v2 v5 gnd com2 1 frame 1 frame v1 v2 v5 gnd com17 v1 v2 v5 gnd com18 v1 figure 23 lcd drive output waveform (2-line character display with 1/18 multiplexing duty ratio)
HD66704 43 power supply for liquid crystal display drive when external power supply is used to supply lcd drive voltage directly from the external power supply without using the internal booster, circuits should be connected as shown in figure 24. here, contrast can be adjusted through the ct bits of the contrast control instruction. when the operational amplifier is used (amp = 1), be sure to boost the external power supply vlcd to double v cc and set the bt bit to 0. when an operational amplifier is not used (amp = 0), vlcd must be equal to or higher than v cc . the HD66704 incorporates a voltage-follower operational amplifier for each v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of lcd drive voltages. thus, potential differences between vlcd and v1 and between v5 and gnd must be 0.1 v or higher. if the display quality is poor, place a capacitor of about 0.1 f to 0.47 f between each internal operational amplifier output v1out to v5out and gnd and stabilize the output level of the operational amplifier. adjust the value of the capacitor if necessary after visually checking the display quality on the lcd panel. c1+ v lcd v lcd vr r 0 r r r gnd booster r HD66704 v2out v5out + lcd driver seg1 to seg80 com1 to com18 v1 v3 v4 v2 v5 gnd c1C c2+ c2C vlout (note 2) 0.1 f to 0.47 f(*) (b characteristics) gnd v1out v3out v4out + + + + C + C + C + C + C + figure 24 external power supply circuit for lcd drive voltage generation
HD66704 44 notes: 1. adjust the value of the capacitor (*) after it is mounted on the lcd panel. 2. the capacitor to be connected to v1out to v5out must be able to withstand the vlcd voltage. consider changes in the vlcd voltage and the breakdown voltage of the capacitor.
HD66704 45 when an internal booster is used to supply lcd drive voltage using the internal booster, circuits should be connected as shown in figure 25. here, contrast can be adjusted through the ct bits of the contrast adjustment register. the reference power-supply voltage in the booster is between v cc and gnd. be careful when lowering the v cc voltage since the lcd drive current flows on the v cc and gnd pins. the HD66704 incorporates a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different lcd drive voltages. thus, the potential differences between vlcd and v1 and between v5 and gnd must be 0.1 v or higher. if the display quality is poor, place a capacitor of about 0.1 f to 0.47 f between each internal operational amplifier output v1out to v5out and gnd and stabilize the output level of the operational amplifier. adjust the value of the capacitor if necessary after visually checking the display quality on the lcd panel.
HD66704 46 v lcd vr r 0 r r r C + gnd c1+ c1C vcc + vlout gnd + c2+ c2- + booster r HD66704 v2out v5out + lcd driver seg1 to seg80 com1 to com18 v1 v3 v4 v2 v5 gnd gnd vcc v1 out v3out v4out + + + + (note 6) 0.1 f to 0.47 f(*) (b characteristics) (note 6) 0.47 f to 1 f (b characteristics) (note 5) 0.47 f to 1 f (b characteristics) (note 2), (note 5) 0.47 f to 1 f (b characteristics) C + C + C + C + figure 25 internal booster circuit for lcd drive voltage generation notes: 1. the reference voltage input (v cc ) must be adjusted so that the output voltage after boosting will not exceed the absolute maximum rating for the lcd power-supply voltage (6.5 v). particularly, cares must be needed for triple boosting. 2. when using up to the double booster, no capacitors are required between c2+ and c2-. 3. if polarized capacitors are used, connect them correctly. 4. adjust the value of the capacitor (*) after it is mounted on the lcd panel. 5. the capacitor to be connected to c1+/c1- and c2+/c2- must be resistant to the v cc voltage. 6. the capacitor to be connected to vlout and v1out to v5out must be resistant to n-times or more of the v cc voltage (n: boosting factor). consider the change of the v cc voltage and the resistant voltage of the capacitor.
HD66704 47 liquid crystal display drive bias selector circuit an optimum liquid crystal display bias value can be selected using bs1-0 bits, according to the liquid crystal drive duty ratio setting (nl2-0 bits). liquid crystal display drive duty ratio and bias value can be displayed while switching software applications to match the lcd panel display status. the optimum bias value calculated using the following expression is an ideal value where the optimum contrast is obtained. driving by using a lower value than the optimum bias value provides lower contrast and lower liquid crystal display voltage (potential difference between v1 and gnd). when the liquid crystal display voltage is insufficient even if a triple booster is used or output voltage is lowered because the battery life has been reached, the display can be made easier to see by lowering the liquid crystal bias. the liquid crystal display can be adjusted by using the contrast adjustment register (ct4-0 bits) and selecting the booster output level (bt bit). optimum bias value for 1/n duty ratio drive voltage = n + 1 1 table 22 lcd drive duty ratio and optimum drive bias values lcd drive duty ratio (nl2-0 set value) 1/18 (nl2-0 = 101/110) 1/11 (nl2-0 = 100) 1/4 (nl2-0 = 010) 1/3 (nl2-0 = 010) 1/2 (nl2-0 = 000) optimum drive bias value (bs1-0 set value) 1/5 or 1/4 (bs1-0 = 00, 01) 1/4 (bs1-0 = 01) 1/3 (bs1-0 = 10) 1/3 or 1/2 (bs1-0 = 10, 11)
HD66704 48 note: r = reference resistor v r v1 v2 v3 v4 v5 r r r r r i) 1/5 bias (bs1-0 = "00") v lcd gnd gnd v r v1 v2 v3 , v4 v5 r r r r ii) 1/4 bias (bs1-0 = "01") v lcd gnd gnd v r v1 , v4 v2 , v5 r r iv) 1/2 bias (bs1-0 = "11") v lcd v3 , gnd gnd v r v1 v2 , v4 v3 , v5 r r r iii) 1/3 bias (bs1-0 = "10") v lcd gnd gnd figure 26 liquid crystal display drive bias circuit
HD66704 49 contrast adjuster contrast for an lcd can be adjusted by varying the liquid-crystal drive voltage (potential difference between vlcd and v1) through the ct bits of the contrast control instruction (electron volume function). see figure 27 and table 23. the value of a variable resistor (vr) can be adjusted within a range from 0.1 r through 2.5 r, where r is a reference resistance obtained by dividing the total resistance between vlcd and v1. the HD66704 incorporates a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different liquid-crystal drive voltages. thus, ct4-0 bits must be adjusted so that the potential differences between vlcd and v1 and between v5 and gnd are 0.1 v or higher when the lcd is driven. v lcd vr r r r 0 r r gnd HD66704 ct v1 v2 v3 v4 v5 gnd C + C + C + C + C + figure 27 contrast adjuster
HD66704 50 table 23 contrast-adjust bits (ct) and variable resistor values 0 ct3 0 ct2 0 ct1 0 ct0 ct set value variable resistor value (vr) 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 2.5 x r 01 1 1 0 ct4 0 0 0 0 0 0 0 100 1 2.3 x r 0 101 0 2.2 x r 0 potential difference between v1 and gnd display color (small) (large) (light) (deep) 101 2.1 x r 0 1 1 0 0 2.0 x r 0 1 1 0 1 1.9 x r 0 1 11 0 1.8 x r 0 11 1 1 1.7 x r 0 0000 1.6 x r 1 0001 1.5 x r 1 0 0 1 0 1.4 x r 1 0 0 1 1 1.3 x r 1 01 0 0 1.2 x r 1 01 0 1 1.1 x r 1 01 1 0 1.0 x r 1 0 1 1 1 0.9 x r 1 1 0 0 0 0.8 x r 1 100 1 0.7 x r 1 101 0 0.6 x r 1 101 1 0.5 x r 1 11 0 0 0.4 x r 1 1 1 0 1 0.3 x r 1 1 1 1 0 0.2 x r 1 1 1 1 1 0.1 x r 1 100 0 2.4 x r 0 1
HD66704 51 table 24 contrast adjustment per bias drive voltage lcd drive voltage: vdr 5 x r + vr 5 x r x (v lcd - gnd) - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : 0.667 x (v lcd -gnd) v dr 0.980 x (v lcd -gnd) x (v lcd -gnd) 0.4 [v] x (v lcd -gnd) 0.4 [v] 5 x r + vr vr r 5 x r + vr : 0.615 x (v lcd -gnd) v dr 0.976 x (v lcd -gnd) x (v lcd -gnd) 0.4 [v] x (v lcd -gnd) 0.4 [v] 4 x r + vr vr r 4 x r + vr : 0.545 x (v lcd -gnd) v dr 0.968 x (v lcd -gnd) x (v lcd -gnd) 0.4 [v] x (v lcd -gnd) 0.4 [v] 3 x r + vr vr r 3 x r + vr : 0.444 x (v lcd -gnd) v dr 0.952 x (v lcd -gnd) x (v lcd -gnd) 0.4 [v] x (v lcd -gnd) 0.4 [v] 2 x r + vr vr r 2 x r + vr 1/5 bias driver 1/4 bias driver 1/3 bias driver 1/2 bias driver 4 x r + vr 4 x r x (v lcd - gnd) bias contrast adjustment range 3 x r + vr 3 x r x (v lcd - gnd) 2 x r + vr 2 x r x (v lcd - gnd) note: the values in table 24 are ideal. actual values will vary from product to product. mount the adjuster on the lcd panel, and select the bias and contrast.
HD66704 52 lcd panel interface the HD66704 has a function for changing the common driver/segment driver output shift direction using the cms bit and sgs bit to meet the chip mounting positions of the HD66704. this is to facilitate the interface wiring to the lcd panel with cog installed. hitachi ltd. HD66704 new de front of chip (cms = 0, sgs = 1) seg80/1 seg1/80 com18/1 com1/18 hitachi ltd. HD66704 new de back of chip (cms = 0, sgs = 0) seg80/1 seg1/80 com18/1 com1/18 hitachi ltd. HD66704 new de back of chip (cms = 1, sgs = 1) seg80/1 seg1/80 com18/1 com1/18 hitachi ltd. HD66704 new de front of chip (cms = 1, sgs = 0) seg80/1 seg1/80 com18/1 com1/18 figure 28 pattern wiring for 2-line character display hitachi ltd. HD66704 new device front of chip (cms = 0, sgs = 1) seg80/1 seg1/80 com18/1 com1/18 figure 29 pattern wiring for 1-line 32-character display at 1/18-duty ratio
HD66704 53 cgrom bank switching function the HD66704 incorporates two pages of cgrom. switching the memory bank using the cgrom bank- switching bit (rom) can display a total of 432 font patterns. multinational fonts, special symbols, and icons can be displayed. note that the number of fonts simultaneously displayed is cgrom: 240 + cgram: 2 when memory bank 0 is selected, and cgrom: 192 + cgram: 2 when memory bank 1 is selected. font displays for cgram (1) to (2) are used in common with memory bank 0 and memory bank 1. table 25 cgrom bank switching character code memory bank 0 (rom = 0) memory bank 1 (rom = 1) "00"h to "0f"h cgram (1) to (2) cgram (1) to (2) "10"h to "1f"h cgrom (1) to (16) cgram (1) to (2) "20"h to "2f"h cgrom (17) to (32) cgrom (241) to (256) "30"h to "3f"h cgrom (33) to (48) cgrom (257) to (272) "40"h to "4f"h cgrom (49) to (64) cgrom (273) to (288) "50"h to "5f"h cgrom (65) to (80) cgrom (289) to (304) "60"h to "6f"h cgrom (81) to (96) cgrom (305) to (320) "70"h to "7f"h cgrom (97) to (112) cgrom (321) to (336) "80"h to "8f"h cgrom (113) to (128) cgram (1) to (2) "90"h to "9f"h cgrom (129) to (144) cgram (1) to (2) "a0"h to "af"h cgrom (145) to (160) cgrom (337) to (352) "b0"h to "bf"h cgrom (161) to (176) cgrom (353) to (368) "c0"h to "cf"h cgrom (177) to (192) cgrom (369) to (384) "d0"h to "df"h cgrom (193) to (208) cgrom (385) to (400) "e0"h to "ef"h cgrom (209) to (224) cgrom (401) to (416) "f0"h to "ff"h cgrom (225) to (240) cgrom (417) to (432)
HD66704 54 double-height display the HD66704 can generate a double-height display of the characters on the first line when the dl bit is set to 1. all the incorporated font characters set in the cgrom and cgram can be doubled in height, allowing easy recognition. note that there should be no space between the lines for double-height display (figure 30). dl = 1 (1st line: double-height display) figure 30 double-height display
HD66704 55 line-cursor display in the character mode, the HD66704 can assign a cursor attribute to an entire line corresponding to the address counter value by setting the lc bit to 1. one of three line-cursor modes can be selected: a black- white reversed cursor (b/w = 1), an underline cursor (c = 1), and a blinking cursor (b = 1). the cycle for a blinking cursor is 32 or 64 frames according to the bl bit setting. these line cursors are suitable for highlighting an index and/or marker, or for indicating an item in a menu with a cursor or an underline. table 26 address counter value and line-cursor display address counter value (ac) selected line for line-cursor display 00h to 13h entire 1st line (16 characters) 20h to 33h entire 2nd line (16 characters)
HD66704 56 i) normal display (lc = 0) iii) underline cursor display (lc = 1, c = 1) iv) blinking cursor display (lc = 1, b = 1) alternates every 32 or 64 frames ii) black-white reversed cursor display (lc = 1, b/w = 1) figure 31 examples of cursor display
HD66704 57 segment display function using some of the ddram area allows the display of 160 segments in two-row character mode, 240 segments in one-row character mode, and 320 segments in segment mode. these segments are displayed without blink control by setting the sb bit to 0. data for the segment display is one bit/segment and only the upper four bits (d7-d4) of locations in the ddram are used. after display data has been written to the upper four bits of a given byte, the address counter (ac) is automatically incremented or decremented. in this case (sb = 0), the lower four bits (d3-d0) are ignored (see table 27). when the sb bit is set to 1, segments are displayed with blink control. data for the segment display is now two bits/segment. the two bits control whether segments are light or dark, and the blinking of segments (see table 28). during blinking, the segment goes dark or light for 32 or 64 frames. the bl bit selects the number of frames. in normal display mode, the blink activates the segment. in inverse display mode, the blink deactivates the segment. a combination of normal and inverse display modes with blinking can display motion in sets of segments. when the device is in character display mode (nl2 = 1) and a character code is written to the ddram, the sb bit must be 1 when data is written to the ddram. table 27 relationship bet ween data in the ddram and segment display, in segment mode without blinking (sb = 0) d5 d4 0 1 ddram data setting note: only the upper four bits of data in the ddram are used to display segments. settings in the lower four bits are invalid and are ignored. segment lcd-display control 0 (always light) 1 (always dark) d6 d7 0 1 0 1 0 1 seg1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 73, 77 seg2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 78 seg3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59, 63, 67, 71, 75, 79 seg4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80 segment driver
HD66704 58 table 28 relationship between data in the ddram and segment display, in segment mode with blinking (sb = 1) d3 d2 d1 d0 00 01 10 11 ddram data setting note: the bl bit selects the blink cycle and the cycle is each 32 (bl = 0) or 64 frames (bl = 1). segment lcd-display control 0 (always light) blinking display in inverse mode 1 (always dark) blinking display d4 d5 d6 d7 00 01 10 11 00 01 10 11 00 01 10 11 seg1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 73, 77 seg2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 78 seg3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59, 63, 67, 71, 75, 79 seg4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80 segment driver
HD66704 59 indicates alternation every 32 or 64 frames figure 32 example of a segment-based display
HD66704 60 blink synchronization function issuing a blink synchronization instruction (70h) resets the blink cycle counter and starts a blink by activating the segment. it can be, for example, issued every second to make the colon on a clock display indicate the passage of seconds. when a blink cycle is started by blink synchronization in inverse display mode, the segment will be de-activated. when the frame frequency exceeds 96 hz, make the blink take 64 frames, by setting the bl bit to 1. when using the built-in r-c oscillator circuit, the dispersion of the frame frequency will match that of the r-c oscillation frequency. note that the oscillation frequency is dispersed by 30 % at least when an r-c oscillator is configured with the built-in rf resistance. 64 frames 36 frames blink synchronization blink synchronization blink synchronization blink synchronization 1 second blink cycle counter 1 second 1 second figure 33 blink synchronization function blinking a colon to indicate seconds figure 34 usage example of blink synchronization
HD66704 61 sleep mode setting the sleep mode bit (slp) to 1 puts the HD66704 in the sleep mode, where the device stops all internal display operations except for the r-c oscillator, thus reducing current consumption. specifically, lcd drive is completely halted. here, all the seg (seg1 to seg80) and com (com1 to com18) pins output the gnd level, resulting in no drive voltage being applied to any lcd cell. if the amp bit is set to 0 in the sleep mode, the lcd drive power supply can be turned off, reducing the total current consumption of the lcd module. standby mode setting the standby mode bit (stb) to 1 puts the HD66704 in the standby mode, where the device stops completely, halting all internal operations including the r-c oscillator, thus further reducing current consumption compared to that in the sleep mode. here, all the seg (seg1 to seg80) and com (com1 to com18) pins output the gnd level, resulting that no drive voltage is applied to each lcd cell. if the amp bit is set to 0 in the standby mode, the lcd drive power supply can be turned off. during the standby mode, no instructions can be accepted other than the start-oscillator instruction. to cancel the standby mode, issue the start oscillator instruction to stabilize r-c oscillation before setting the stb bit to 0. set standby mode: stb = 1 standby mode issue the start-oscillator instruction wait at least 10 ms cancel standby mode: stb = 0 turn on the lcd drive power supply: amp = 1 turn off the lcd power supply: amp = 0 figure 35 procedure for setting and canceling standby mode
HD66704 62 absolute maximum ratings item symbol unit value notes* power supply voltage (1) v cc v C0.3 to +7.0 1, 2 power supply voltage (2) v lcd C gnd v C0.3 to +7.0 1, 3 input voltage vt v C0.3 to v cc + 0.3 1 operating temperature topr c C40 to +85 1, 4 notes: 1. if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristics limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. 2. v cc gnd must be maintained. 3. v lcd v cc must be maintained. 4. for the dc/ac characteristics for bare die products, specified up to 85c. dc characteristics (v cc = 1.8 to 5.5 v, ta = C40 to +85c* 1 ) item symbol min typ max unit test condition notes input high voltage v ih 0.7 v cc v cc v 2, 3 input low voltage v il C0.3 0.15 v cc vv cc = 1.8 to 2.7 v 2, 3 C0.3 0.15 v cc vv cc = 2.7 to 5.5 v 2, 3 driver on resistance (com pins) r com 3 20 k ? id = 0.05 ma, v lcd = 5 v 4 driver on resistance (seg pins) r seg 3 30 k ? id = 0.05 ma, v lcd = 5 v 4 input leakage current i li C1 1 a vin = 0 to v cc current consumption during normal operation (v cc Cgnd) i op 20 35 a r-c oscillation, v cc = 3 v, ta = 25c, f osc = 32 khz (1/17 duty) 5, 6 current consumption during sleep mode (v cc Cgnd) i sl (11) a r-c oscillation, v cc = 3 v, ta = 25c, f osc = 32 khz (1/17 duty) 5, 6 current consumption during standby mode (v cc Cgnd) i st 0.1 5 a v cc = 3 v, ta = 25c 5, 6 lcd drive power supply current (v lcd Cgnd) i lcd 1735av lcd C gnd = 5.5 v, ta = 25c, f osc = 32 khz, 1/5 bias 6 lcd drive voltage (v lcd C gnd) v lcd 3.0 6.5 v v lcd v cc , amp = 0 (v lcd vlout, amp = 1) 7 note: for the numbered notes, refer to the electrical characteristics notes section following these tables.
HD66704 63 booster characteristics item symbol min typ max unit test condition notes double-boost output voltage (vloutCgnd) v up2 5.5 5.9 6.0 v v cc = 3.0 v, i o = 30 a, c = 1 f, f osc = 32 khz, ta = 25c 11 triple-boost output voltage (vloutCgnd) v up3 6.1 6.5 6.6 v v cc = 2.2 v, i o = 30 a, c = 1 f, f osc = 32 khz, ta = 25c 11 range of boosting output voltage (vloutCgnd) v up2 v cc 6.5 v double boost 11 v up3 v cc 6.5 v triple boost 11 note: for the numbered notes, refer to the electrical characteristics notes section following these tables. ac characteristics (v cc = 1.8 to 5.5 v, ta = C40 to +85c* 1 ) clock characteristics (v cc = 1.8 to 5.5 v) item symbol min typ max unit test condition notes external clock frequency fcp 15 32 100 khz 8 external clock duty ratio duty 45 50 55 % 8 external clock rise time t rcp 0.2 s 8 external clock fall time t fcp 0.2 s 8 external rf oscillation frequency t osc1 25 32 40 khz rf = 620 k ? , v cc = 3 v 9 internal rf oscillation frequency t osc2 19 32 45 khz r1-osc2: short- circuiting, v cc = 3 v 10 note: for the numbered notes, refer to the electrical characteristics notes section following these tables.
HD66704 64 4-bit bus interface timing characteristics (v cc = 1.8 to 2.7 v) item symbol min typ max unit test condition enable cycle time t cyce 800 ns figure 41 enable high-level pulse width pw eh 150 ns figure 41 enable low-level pulse width pw el 300 ns figure 41 enable rise/fall time t er , t ef 25 ns figure 41 setup time (rs to e, cs*) t ase 60 ns figure 41 address hold time t ahe 20 ns figure 41 write data set-up time t dswe 60 ns figure 41 write data hold time t he 20 ns figure 41 (v cc = 2.7 to 5.5 v) item symbol min typ max unit test condition enable cycle time t cyce 500 ns figure 41 enable high-level pulse width pw eh 80 ns figure 41 enable low-level pulse width pw el 250 ns figure 41 enable rise/fall time t er , t ef 25 ns figure 41 setup time (rs to e, cs*) t ase 60 ns figure 41 address hold time t ahe 20 ns figure 41 write data set-up time t dswe 60 ns figure 41 write data hold time t he 20 ns figure 41
HD66704 65 clock-synchronized serial interface timing characteristics (v cc = 1.8 to 5.5 v) (v cc = 1.8 to 2.7 v) item symbol min typ max unit test condition serial clock cycle time t scyc 0.5 20 s figure 42 serial clock high-level width t sch 230 ns figure 42 serial clock low-level width t scl 230 ns figure 42 serial clock rise/fall time t scf , t scr 20 ns figure 42 chip select set-up time t csu 60 ns figure 42 chip select hold time t ch 200 ns figure 42 serial input data set-up time t sisu 100 ns figure 42 serial input data hold time t sih 100 ns figure 42 (v cc = 2.7 to 5.5 v) item symbol min typ max unit test condition serial clock cycle time t scyc 0.2 20 s figure 42 serial clock high-level width t sch 80 ns figure 42 serial clock low-level width t scl 80 ns figure 42 serial clock rise/fall time t scf , t scr 20 ns figure 42 chip select set-up time t csu 60 ns figure 42 chip select hold time t ch 200 ns figure 42 serial input data set-up time t sisu 40 ns figure 42 serial input data hold time t sih 40 ns figure 42 reset timing characteristics (v cc = 1.8 to 5.5 v) item symbol min typ max unit test condition reset low-level width t res 1 ms figure 43
HD66704 66 electrical characteristics notes 1. for bare die products, specified up to +85 c. 2. the following two circuits are i/o pin configurations (figure 36). pmos nmos vcc gnd pmos nmos vcc pins: reset*, rs/cs*, e/scl, sda, db3-db1, db0/id, osc1, im2/1, test pins: osc2 gnd figure 36 i/o pin configuration 3. the test pin must be grounded and the im2/1 pin must be grounded or connected to v cc . when using the clock-synchronized serial interface, db3-1 and db0/id must be grounded or connected to v cc . 4. applies to the resistor value (rcom) between power supply pins v1out, v2out, v5out, gnd and common signal pins, and resistor value (rseg) between power supply pins v1out, v3out, v4out, gnd and segment signal pins, when current id is flown through all driver output pins. 5. this excludes the current flowing through the input/output units. the input level must be fixed to v cc or gnd because through current increases if the cmos input is left floating. 6. the following shows the relationship between the operation frequency and current consumption (figure 37). r-c oscillation frequencies: fosc (khz) 30 20 10 0 lop ( a) vcc = 3 v 0 display on (typ.) sleep (typ.) 30 20 10 0 i lcd ( a) vcc = 2 v, fosc = 32 khz lcd drive voltages: v lcd (v) 4.0 5.0 6.0 standby (typ.) 20 10 30 40 50 typ. figure 37 relationship between the operation frequency and current consumption
HD66704 67 7. each com and seg output voltage is within 0.15 v of the lcd voltages (v cc , v1, v2, v3, v4, and v5) when there is no load. 8. applies to the external clock input (figure 38). oscillator osc1 open osc2 t rcp t fcp th tl 0.7vcc 0.5vcc 0.3vcc duty = th+tl th 100% figure 38 external clock supply 9. applies to the internal oscillator operations using external oscillation resistor rf (figure 39). osc1 osc2 rf since the oscillation trequency varies depending on the osc1 and isc2 pin capacitance, the wiring length to these pins should be minimized. figure 39 internal oscillation table 29 external resistance value and r-c oscillation frequency (referential data) external r-c oscillation frequency: fosc resistance (rf) vcc = 1.8 v vcc = 2.2 v vcc = 3.0 v vcc = 4.0 v vcc = 5.0 v 390 k ? 40 khz 45 khz 48 khz 50 khz 51 khz 510 k ? 33 khz 36 khz 38 khz 40 khz 41 khz 560 k ? 30 khz 33 khz 35 khz 36 khz 37 khz 620 k ? 28 khz 30 khz 32 khz 33 khz 33 khz 680 k ? 26 khz 29 khz 30 khz 31 khz 31 khz 750 k ? 24 khz 27 khz 28 khz 29 khz 29 khz 10. note that the oscillation and frame frequencies are changed by 30% or more when the internal oscillation resistance is used.
HD66704 68 11. booster characteristics test circuits are shown in figure 40. * vup2 = vlout - gnd * vup3 = vlout - gnd 3.0 2.5 2.0 1.5 3.0 4.0 5.0 6.0 (i) relation between the obtained voltage and input voltage vcc (v) vup2 (v) typ. test condition: fosc = 32 khz, ta = 25 c 2.5 2.0 1.5 1.0 3.0 4.0 typ. test condition: fosc = 32 khz, ta = 25 c vup3 (v) vcc (v) test condition: vcc = 3 v, fosc = 32 khz, io = 30 a (ii) relation between the obtained voltage and temperature test condition: vcc = 2.2 v, fosc = 32 khz, io = 30 a double boosting triple boosting double boosting triple boosting ta ( c) ta ( c) vup2 (v) 100 60 20 0 C20 C60 5.0 5.5 6.0 6.5 typ. vup3 (v) 100 60 20 0 -20 -60 6.0 6.5 7.0 typ. referential data triple boosting double boosting gnd vcc 1 f c1+ c1C vlout + v lcd c2+ c2C 1 f + gnd vcc 1 f c1+ c1C vlout + v lcd c2+ c2C 1 f + 1 f + 5.0 6.0 7.0 figure 40 booster
HD66704 69 (iii) relation between the obtained voltage and capacitance test condition: vcc = 3.0 v, fosc = 32 khz, io = 30 a test condition: vcc = 2.2 v, fosc = 32 khz, io = 30 a test condition: vcc = 3.0 v, fosc = 32 khz, ta = 25 c test condition: vcc = 2.2 v, fosc = 32 khz, ta = 25 c vup3 (v) double boosting triple boosting c ( f) c ( f) vup2 (v) (iv) relation between the obtained voltage and current io ( a) io ( a) vup2 (v) 200 150 100 50 0 4.5 5.0 5.5 6.0 6.5 7.0 typ. vup3 (v) 200 150 100 50 0 5.0 5.5 6.0 6.5 7.0 typ. double boosting triple boosting 1.5 1.0 0.5 5.0 5.5 6.0 6.5 typ. 7.0 4.5 1.5 1.0 0.5 5.0 5.5 6.0 6.5 typ. 7.0 figure 40 booster (cont)
HD66704 70 timing characteristics 4-bit bus operation rs e db0 to db3 write data v ih v ih v ih t er t dswe t he t cyce t ef t ase t ahe v il v il v il v il pw eh pw el v ih v il v ih v il v ih v il figure 41 4-bit bus timing clock-synchronized serial operation cs* scl sda input data input data start: s t csu t csr t sch t scl t scyc t scf t sih t sisu t ch v ih v ih v ih v ih v ih v ih v il v il v il v il v il v il v il v il end: p figure 42 clock-synchronized serial interface timing
HD66704 71 reset operation reset* v il v il t res figure 43 reset timing
HD66704 72 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: (03) 3270-2111 fax: (03) 3270-5109 copyright ? hitachi, ltd., 2001. all rights reserved. printed in japan. hitachi asia ltd. hitachi tower 16 collyer quay #20-00 singapore 049318 tel : <65>-538-6533/538-8577 fax : <65>-538-6933/538-3877 url : http://semiconductor.hitachi.com.sg url http://www.hitachisemiconductor.com/ hitachi asia ltd. (taipei branch office) 4/f, no. 167, tun hwa north road hung-kuo building taipei (105), taiwan tel : <886>-(2)-2718-3666 fax : <886>-(2)-2718-8180 telex : 23222 has-tp url : http://www.hitachi.com.tw hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel : <852>-(2)-735-9218 fax : <852>-(2)-730-0281 url : http://semiconductor.hitachi.com.hk hitachi europe gmbh electronic components group dornacher stra?e 3 d-85622 feldkirchen postfach 201,d-85619 feldkirchen germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi europe ltd. electronic components group whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 585200 hitachi semiconductor (america) inc. 179 east tasman drive san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to: colo p hon 5.0

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